AMD Talks Details on K10

[Kougar]

Lots of good details, both some new and some old in this 1 page article.

Guiseppe Amato gives another overview on the high points of AMD's next-generation CPU architecture


Yesterday, AMD held a press presentation in Munich, Germany to update journalists about its upcoming K10 processor. AMD's Giuseppe Amato, Technical Director Sales and Marketing EMEA, had a few minutes to talk about the architecture at length.

The integrated memory controller (IMC) will get a few new features in the K10 core. When utilizing multiple memory modules, along with proper BIOS implementation and mainboard routing, the IMC can access memory in 64-bit channels (72-bit if you use ECC). This way it is possible to read and write data simultaneously, or improve efficiency for irregular access patterns which increasingly occur in a quad-core environment. This feature is available on AM2+ and F+ boards; on "old“ socket AM2 and F boards the usual 128-bit dual-channel mode is available.

Due to split power planes, the IMC can be clocked down independently of the CPU cores, along with reduced voltage. This also enables CPU overclocking without touching the memory frequency, something that may appeal to enthusiasts. These features are again dependent on Socket AM2+ and F+ platforms.

Amato explained how the quad-core design benefits from the internal crossbar switch the backbone of communication inside the K10 CPU. With Intel's current quad-core design there are cases where data needs to travel over the FSB -- in AMDs case all inter-CPU communication takes place on-die.

Skip to the full article at http://www.dailytech.com/AMD+Talks+Details+on+K10/article6918.htm (http://www.dailytech.com/AMD+Talks+Details+on+K10/article6918.htm)

[PP Mguire]

Why are they going backwards from 128-bit to 64? Dosent make any sense.

[Kougar]

That's the trick. Instead of having a single 128-bit lane road to the RAM, they now have at least two 64-bit roads to the RAM... which means they can send read/write requests while the RAM is sending information back to the CPU. It's kinda like going to the grocery store every Friday, instead of going only once a month if that makes sense. ;)

If you have 4 cores each sending read/write requests, it's faster to have split lanes to the RAM. Otherwise 3 cores would have to wait on the 4th to send/receive data before they could take turns doing the same. This should give them a an advantage over Intel's chips as well I believe.

[liqnit]

what i miss is the support for DDR3\DDR4?

[PP Mguire]

That's the trick. Instead of having a single 128-bit lane road to the RAM, they now have at least two 64-bit roads to the RAM... which means they can send read/write requests while the RAM is sending information back to the CPU. It's kinda like going to the grocery store every Friday, instead of going only once a month if that makes sense.The 128-bit lane is supposed to be two channels. One up and one down. So basicaly its 2 64-bit lanes that can read and write simotaneously, or in simple 2 64-bit DC lanes? Or am i missing something. Cause what you said and what dual channel ram is supposed to be sounds the same.

[liqnit]

in QuadCore you need 4 Lanes(DC) by going 64Bit if i undersatnd correctly you can give each core a DC

[Kougar]

I assumed it was 2 64-bit lanes, but if they have two 128bit channels then it would actually be 4 64-bit lanes... one per core as Liqnit said. :)

I haven't actually dug up any info though, it is just how I understood the article to be stating it in its general way, however many actual channels.

[PP Mguire]

I assumed it was 2 64-bit lanes, but if they have two 128bit channels then it would actually be 4 64-bit lanes... one per core as Liqnit said.Now like i was saying, this makes more sense. Not drop back down to a single 64-bit channel. One for each core.

[AlabamaCajun]

What AMD is doing is opening the two 64bit channnels up for split access or both for 128. There is only 128 bits of datapath to the ram controller. In thise case the RAM controller has been improved to split into 2 for simutaneous in and out transfers. The HT IO channels already do this. The RAM controller is connected to the cache through a multi-path crossbar interface allowing multiple data transfers simultaneously such as a cloverleaf on an interstate does for 4 lanes of traffic. This allows the cores to send data from cpu cache to ram or IO, to/from ram to io. Yes IO transfers can Direct Memory Access without the cores once instructed without data going to the L2/L3 cache or the Core.
L3 Cache is going bring some nice improvements for multi tasking/ SMP.
* Provide a holding area for storing data that has been forced out of L2 cache from an overflow.
* Provide a shared memory buffer between cores
* Additional buffering for off-die RAM (dimms).
* Mostly on multi-socket systems, L3 will also provide buffering area for chip to chip and IO transfers.

[PP Mguire]

Thank you for your information. Props! Like i thought, its still the same dual channel memory but they improved upon the passage between it. Thanx a bunch.