sushrukh
07-04-2007, 03:44 PM
One of the greatest challenges facing the designers of many-core processors is resource contention. The chart below visually lays out the problem of resource contention, but for most of us the idea is intuitively easy to grasp: more cores and more simultaneous threads means more contention for shared resources, specifically cache space and memory bandwidth.
http://media.arstechnica.com/articles/paedia/cpu/cache-mem-many-core.media/resource-graph.gif
Resource contention versus core and thread count
As Moore's Law increases, the amount of parallel hardware and the number of threads that can access a single, shared resource, this problem will continue to grow. Indeed, resource contention challenges have the potential to scale fairly well with increases in core and thread counts, so chip multiprocessor (CMP) designers have been working on ways to address this issue since the very start of the dual-core era.
In the present article, I'll take a look at the issue of resource contention and at one of Intel's proposed methods for overcoming this challenge: the quality-of-service-aware memory hierarchy.
QoS and the memory hierarchy
Intel's solution to the resource contention problem—a solution with a very long pedigree in everything from networks to the power grid—is to build a framework for enforcing priority-based quality of service (QoS) in the memory hierarchy. This solution was described and evaluated in a recent ACM SIG presentation entitled "QoS Policy and Architecture for Cache/Memory in CMP Platforms."
The basic idea goes as follows: A hardware/software mechanism is provided so that a user or administrator can assign running threads one of two priority levels, either low (1) or high (0). High-priority threads, which are presumably more critical than lower-priority threads, are then given more cache space and more memory bandwidth than low-priority threads. A special hardware unit keeps track of the resources that each thread is using in real time and makes tweaks and adjustments to the cache and memory unit so that the overall result is that the high-priority threads keep the upper hand over the low-priority threads.
http://media.arstechnica.com/articles/paedia/cpu/cache-mem-many-core.media/qos.gif
The QoS-aware memory hierarchy
More here at :- http://arstechnica.com/articles/paedia/cpu/cache-mem-many-core.ars
http://media.arstechnica.com/articles/paedia/cpu/cache-mem-many-core.media/resource-graph.gif
Resource contention versus core and thread count
As Moore's Law increases, the amount of parallel hardware and the number of threads that can access a single, shared resource, this problem will continue to grow. Indeed, resource contention challenges have the potential to scale fairly well with increases in core and thread counts, so chip multiprocessor (CMP) designers have been working on ways to address this issue since the very start of the dual-core era.
In the present article, I'll take a look at the issue of resource contention and at one of Intel's proposed methods for overcoming this challenge: the quality-of-service-aware memory hierarchy.
QoS and the memory hierarchy
Intel's solution to the resource contention problem—a solution with a very long pedigree in everything from networks to the power grid—is to build a framework for enforcing priority-based quality of service (QoS) in the memory hierarchy. This solution was described and evaluated in a recent ACM SIG presentation entitled "QoS Policy and Architecture for Cache/Memory in CMP Platforms."
The basic idea goes as follows: A hardware/software mechanism is provided so that a user or administrator can assign running threads one of two priority levels, either low (1) or high (0). High-priority threads, which are presumably more critical than lower-priority threads, are then given more cache space and more memory bandwidth than low-priority threads. A special hardware unit keeps track of the resources that each thread is using in real time and makes tweaks and adjustments to the cache and memory unit so that the overall result is that the high-priority threads keep the upper hand over the low-priority threads.
http://media.arstechnica.com/articles/paedia/cpu/cache-mem-many-core.media/qos.gif
The QoS-aware memory hierarchy
More here at :- http://arstechnica.com/articles/paedia/cpu/cache-mem-many-core.ars