sushrukh
08-10-2007, 11:40 PM
PCI-SIG, the Special Interest Group responsible for PCI Express industry-standard I/O technology, announced today some of the key features of the PCI Express 3.0 interconnection technology, which is due to be deployed in 2010 and will have clock-speed of 8GHz, or 8 gigatransfers per second.
“Experts in the PCIe Electrical Workgroup analyzed both 10GT/s and 8GT/s as target bit rates for the next generation of PCIe architecture, and after careful consideration of several factors, including power, implementation complexity and silicon area, recommended 8GT/s,” said Al Yanes, PCI-SIG chairman.
Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, the data shows that 8GT/s can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full mechanical compatibility and with negligible impact to the PCIe protocol stack.
“This allows us to satisfy the next generation performance requirements for all existing PCIe applications while maintaining backward compatibility, and at the same time broadening the adoption of this pervasive technology into new and emerging applications and usage models,” Mr. Yanes added.
The 8GT/s bit rate represents a doubling of the delivered bandwidth by removing the requirement for the 8b/10b encoding scheme supported in prior versions of PCIe architecture, which imposed a 20% overhead on the raw bit rate. The PCIe 3.0 specification will introduce a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies. The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond, the SIG said.
Link :- http://www.xbitlabs.com/news/other/display/20070808225423.html
“Experts in the PCIe Electrical Workgroup analyzed both 10GT/s and 8GT/s as target bit rates for the next generation of PCIe architecture, and after careful consideration of several factors, including power, implementation complexity and silicon area, recommended 8GT/s,” said Al Yanes, PCI-SIG chairman.
Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, the data shows that 8GT/s can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full mechanical compatibility and with negligible impact to the PCIe protocol stack.
“This allows us to satisfy the next generation performance requirements for all existing PCIe applications while maintaining backward compatibility, and at the same time broadening the adoption of this pervasive technology into new and emerging applications and usage models,” Mr. Yanes added.
The 8GT/s bit rate represents a doubling of the delivered bandwidth by removing the requirement for the 8b/10b encoding scheme supported in prior versions of PCIe architecture, which imposed a 20% overhead on the raw bit rate. The PCIe 3.0 specification will introduce a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies. The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond, the SIG said.
Link :- http://www.xbitlabs.com/news/other/display/20070808225423.html