Das Capitolin
07-01-2006, 08:05 AM
Next-generation Merom notebook processor is going to be releasing in the last week of Aug 2006 (may be 24/8). With the same Intel Core architecture, Merom shares the exactly name with Conroe, called Core 2 Duo. There is no longer a difference on the naming between Desktop and Mobile processor. Smaller Form Factor is the future trend, which mean Desktop and Mobile will no longer be separated. The change in naming would help Intel to push the MoDT(Mobile on Desktop) market, where Santa Rosa platform is one of the plan. There are 3 naming branch among Merom according to its power consumption, Normal “T”(TDP 25-49W), Low Voltage “L”(TDP 15-24W) and Ultra Low Voltage “U”(TDP >14W).
Merom is also separated into two series, 7000 and 5000 series. They are mainly different in the size of L2 Cache. Most of the 7000 series has 4MB L2 Shared Cache, while the 5000 family just has got 2M. Ultra Low Voltage Merom is an exception, where it has only 2M L2 Cache version and will also be named in 7000 series. Merom would exist with Mobile Intel 945 Express and Socket M when it comes. As Yonah is already with VRM11, the existing Centrino Napa platform would support Merom by upgrading the BIOS as well.
In the next Santa Rosa platform, which is a replacement of “Napa Refresh”, Crestline northbridge is introduced together with ICH8M. At that time, Merom will fully support 800MHz FSB but Socket M has been made supported. The replacement to Socket M would be Socket P, also in 478 pin but not compatible with Socket M processor. Without technical improvement, such change is just a marketing decision to make Yonah to fall out of use in Santa Rosa platform. Manufacturers are complained about the change that would make money loss by increased pressure on storage. They are now urging Intel to cancel the decision, making Socket M be available in Santa Rosa platform.
Socket P Merom includes Core 2 Duo T7700(2.4GHz/4MB L2/800MHz FSB), T7500(2.2GHz/4MB L2/800MHz FSB), T7300(2.0GHz/4MB L2/800MHz FSB), T7000(1.8GHz/4MB L2/800MHz FSB), T5500P(1.66GHz/4MB L2/667MHz FSB)P, L7500(1.6GHz/4MB L2/800MHz FSB) and L7300(1.4GHz/4MB L2/800MHz FSB). They are going to be releasing together with Santa Rosa platform, according to NB Roadmap 2007.
Cited: http://www.hkepc.com/bbs/news.php?tid=623694&starttime=0&endtime=0
Conversely, AMD is cutting back their CPU cache's while Intel grows theirs. I wonder what the end-result will be for each chip maker? :confused:
Merom is also separated into two series, 7000 and 5000 series. They are mainly different in the size of L2 Cache. Most of the 7000 series has 4MB L2 Shared Cache, while the 5000 family just has got 2M. Ultra Low Voltage Merom is an exception, where it has only 2M L2 Cache version and will also be named in 7000 series. Merom would exist with Mobile Intel 945 Express and Socket M when it comes. As Yonah is already with VRM11, the existing Centrino Napa platform would support Merom by upgrading the BIOS as well.
In the next Santa Rosa platform, which is a replacement of “Napa Refresh”, Crestline northbridge is introduced together with ICH8M. At that time, Merom will fully support 800MHz FSB but Socket M has been made supported. The replacement to Socket M would be Socket P, also in 478 pin but not compatible with Socket M processor. Without technical improvement, such change is just a marketing decision to make Yonah to fall out of use in Santa Rosa platform. Manufacturers are complained about the change that would make money loss by increased pressure on storage. They are now urging Intel to cancel the decision, making Socket M be available in Santa Rosa platform.
Socket P Merom includes Core 2 Duo T7700(2.4GHz/4MB L2/800MHz FSB), T7500(2.2GHz/4MB L2/800MHz FSB), T7300(2.0GHz/4MB L2/800MHz FSB), T7000(1.8GHz/4MB L2/800MHz FSB), T5500P(1.66GHz/4MB L2/667MHz FSB)P, L7500(1.6GHz/4MB L2/800MHz FSB) and L7300(1.4GHz/4MB L2/800MHz FSB). They are going to be releasing together with Santa Rosa platform, according to NB Roadmap 2007.
Cited: http://www.hkepc.com/bbs/news.php?tid=623694&starttime=0&endtime=0
Conversely, AMD is cutting back their CPU cache's while Intel grows theirs. I wonder what the end-result will be for each chip maker? :confused: