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NVIDIA nForce2 Preview
Date: 2002-07-16 | Author: Gene Janero
and Scott Sherman
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Introduction
Today, NVIDIA is announcing it's latest product, the second generation nForce motherboard chipset to support AMD's Athlon family of Socket-A processors. As we discussed in our review of the original nForce platform, back in December 2001, nForce is a departure from traditional model the all-in-one motherboard solutions. They've incorporated audio, video, network, and high speed bus technology that make it stand above the eMachine class all-in-one motherboards. With this preview, we'll review what NVIDIA has on the nForce platform and what's new with nForce 2. We do not yet have a sample to test, so this preview is based upon press information provided by NVIDIA and on discussion with the NVIDIA staff.
Recap of the nForce Technology
The primary barrier of the existing motherboard architecture on the market has been the over reliance on the CPU for video based geometry calculations, the governing of applications, and the oversight of the peripherals attached to the Southbridge. NVIDIA, last winter, released heir first integrated motherboard chipsets entitled nForce.
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The nForce chipsets entitled Media and Communications Processor (MCP) and Integrated Graphics Processor(IGP) are a departure form the standard Northbridge and Southbridge configurations. NVIDIA, taking advantage of the wealth of technology and small die size construction available, has integrated state of the art audio, video, and networking components on the chipsets. In addition to the inclusion of these items, NVIDIA has bought off on the AMD consortium Hypertransport Technology. This technology, in nForce1, creates a data bus capable of up to 800MB/s between the Northbridge (IGP) and Southbridge (MCP). All of these features are shown on the diagram, at left, which helps identify where NVIDIA has empowered these new chipsets. |
Taking the burden away from the CPU of common and necessary tasks (audio encoding, network translation, etc. which can all be performed concurrently in parallel by hardware) frees up CPU clock cycles to perform other calculations of specific applications or other demands from hardware. This is a profound step in the direction of improving overall system performance. As an example, Scott had noted a minimal CPU load from the integrated 10/100 MAC on his nForce1 board of around 5% vs. a common 25-30% load of PCI network adapters.
To further detail what NVIDIA has included on these chipsets, the following table describes in detail what technology has been integrated:
| Technology | MCP | IGP | Description |
| Hyper-Transport | X | X | This is AMD's high speed interconnection bus interface which controls traffic between the IGP and MCP at 800MB/s (roughly 6 times faster than the PCI bus). |
| StreamThru | X | - | Isochronous aware algorithms that are intended to provide clear and consistent throughput for video, audio, and other communications streams. These algorithms will all but eliminate CPU dependency for network and broadband data streaming. |
| Complete Communications Suite | X | - | HomePNA v.2.0 (Home Phone-line Network Adapter), USB, Software modem, 10/100 Ethernet MAC. |
| Dolby Digital 5.1 real-time encoder | X | - | NVIDIA's APU (Audio Processing Unit) was an industry first, on-board real-time Dolby Digital 5.1 Encoder. The APU supports 2/4/6 channel outputs, DirectX8 3D audio in hardware (32 Hardware Submixers), 256 2D voices, 64 3D voices, and 3D positional audio. |
| TwinBank Memory Architecture | - | X | Unlike industry standard Shared Memory Architecture, a 128-bit wide 266MHz DDR memory path is maintained for the onboard graphics controller, resulting in 4.2GB/s peak memory bandwidth with minimum system latency. This low latency path is maintained by the use of crossbar technology that incorporates dual-independent, 64-bit memory controllers and a single master arbiter. |
| Dynamic Adaptive Speculative Pre-processor(DASP) | - | X | An innovative set of algorithms to reduce CPU system and memory access latency by monitoring CPU access patterns and developing call predictions such that needed data can be pre-staged for lower latency access. |
| Geforce2 GPU | - | X | Last, but not least, a Geforce2 GPU is embedded on the IGP chipset, offering the highest level of 3D graphics performance of any on-die chipset. |
To support this platform, NVIDIA has a Unified Driver and BIOS Architecture that is comprised of a single driver for graphics, IDE, and the complete communications suite. Additionally, the single driver also supports ALL of the current NVIDIA GPUs which will be automatically detected when installed in the AGP slot.
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